Electrical circuits: catalogue

Electrical circuits by Modified Nodal Analysis: resistors, capacitors, inductors, sources and their waveforms, diodes, switches, transformers and controlled sources (Modelica Standard Library device laws); impedances, constant-power loads and power converters (Modelica Buildings Library laws); Joule heating into a thermal network; the reader of OpenModelica circuit exports; balanced AC and DC power flow in per unit (MATPOWER branch model, shunts, voltage-controlled generators) and the MATPOWER case-file reader. How the pieces fit together: Electrical circuits. Every application is set up the same way; see Using noodl.

Import from noodl.apps.electrical and the modules named in each table. The full reference, with every parameter, is in the API reference.

Set-up

Build the model and its starting state and inputs.

Name	What it does	How to call it
build_model noodl.apps.electrical	Assemble the circuit model and return (model, state, drivers).	build_model(circuit, *, phasor=False, frequency=None, temperature=None, learnable=False)
initial_state noodl.apps.electrical	The consistent initial state at time t (s), the start of a transient: every capacitor at its v0, every inductor (and transformer winding) at its i0, sources at their value at t, and the other voltages and currents consistent with those (solve_kwargs, such as Newton's atol and rtol, reach the layer solve).	initial_state(model, drivers, *, t=0.0, **solve_kwargs)
build_power_flow noodl.apps.electrical.power	The AC power flow of net as (model, state, drivers), by the build rules of noodl.apps.electrical.power.build; the network is checked first (check_power_network).	build_power_flow(net, *, frequency=50.0, learnable=False, enforce_q_limits=False)
dc_power_flow noodl.apps.electrical.power	The DC power flow of net as (model, state, drivers), by the build rules of noodl.apps.electrical.power.dc; solve it with solve_power_flow.	dc_power_flow(net)

Network components

Descriptions of the physical objects a network is built from.

Name	What it does	How to call it
Capacitor noodl.apps.electrical	A capacitor i = C dv/dt (C in F), with initial voltage v0 (V). MSL Basic.Capacitor.	Capacitor(name, p, n, C, v0=0.0)
Circuit noodl.apps.electrical	A netlist: devices (the dataclasses of this module) between named nodes, and the ground node (0 V). Construction checks the device types, unique non-empty names, node names on every pin (distinct within a port), scalar parameters, waveforms, switch controls and controlled-source modes, that ground is a pin, and that every node is joined to ground through the devices' port edges (a connectivity check only: a loop of voltage sources or a cut set of current sources passes it and is refused at the solve).	Circuit(devices, ground='0')
Conductor noodl.apps.electrical	A linear conductance i = G v (G in S). MSL Basic.Conductor.	Conductor(name, p, n, G)
ControlledSource noodl.apps.electrical	A linear controlled source: port 1 senses (control="voltage": an open circuit; "current": a short) and port 2 imposes (output="voltage" or "current") gain times the sensed quantity. MSL Basic.VCV, VCC, CCV, CCC.	ControlledSource(name, p1, n1, p2, n2, gain, control, output)
CurrentSource noodl.apps.electrical	An ideal current source i = offset + I unit(t) (A) entering pin p (flowing through the source from p to n); waveform and AC phasor as for VoltageSource. MSL Sources.*Current.	CurrentSource(name, p, n, I, waveform=Constant(), offset=0.0)
Diode noodl.apps.electrical	A junction diode i = Ids (exlin(v / Vt) - 1) + v / R (Ids in A, Vt in V, R the parallel leak in ohm; exponential up to Maxexp, linear above). MSL Semiconductors.Diode. Not usable in an AC analysis.	Diode(name, p, n, Ids=1e-06, Vt=0.04, Maxexp=15.0, R=100000000.0)
IdealTransformer noodl.apps.electrical	An ideal transformer v1 = n v2, i2 = -n i1 (turns ratio n). MSL Ideal.IdealTransformer without magnetisation.	IdealTransformer(name, p1, n1, p2, n2, n)
Inductor noodl.apps.electrical	An inductor v = L di/dt (L in H), with initial current i0 (A). MSL Basic.Inductor.	Inductor(name, p, n, L, i0=0.0)
Resistor noodl.apps.electrical	A linear resistor v = R_actual i, R_actual = R (1 + alpha (T - T_ref)) (R in ohm at T_ref in K, alpha in 1/K); T comes from the builder's temperature driver, else T = T_ref. MSL Basic.Resistor.	Resistor(name, p, n, R, alpha=0.0, T_ref=300.15)
Switch noodl.apps.electrical	An ideal closing switch: closed v = Ron i, open i = Goff v (Ron in ohm, Goff in S); closed where its control value exceeds 0.5. control is a driver key (read at index 0 of its last dimension) or a (key, index) pair. MSL Ideal.IdealClosingSwitch.	Switch(name, p, n, control, Ron=1e-05, Goff=1e-05)
Transformer noodl.apps.electrical	Two coupled windings v1 = L1 di1/dt + M di2/dt, v2 = M di1/dt + L2 di2/dt (H), with initial currents i0 = (i1, i2) (A). MSL Basic.Transformer.	Transformer(name, p1, n1, p2, n2, L1, L2, M, i0=(0.0, 0.0))
VoltageSource noodl.apps.electrical	An ideal voltage source v = offset + V unit(t) (V), unit the waveform. In an AC analysis a Sine source is its steady-state phasor (amplitude V, the waveform's phase) at the analysis frequency, and a Constant source is the magnitude V at phase 0; other waveforms are refused there. MSL Sources.*Voltage.	VoltageSource(name, p, n, V, waveform=Constant(), offset=0.0)
Branch noodl.apps.electrical.power	A line or transformer from from_bus to to_bus: series resistance r, reactance x and total line charging susceptance b (p.u. on base_mva), off-nominal turns ratio ratio at the from end (0 means 1) and phase shift shift_deg (degrees).	Branch(from_bus, to_bus, r, x, b, ratio=0.0, shift_deg=0.0, in_service=True)
Bus noodl.apps.electrical.power	A bus: its id, kind (one of BUS_KINDS), voltage magnitude vm (p.u.) and angle va_deg (degrees) as stated in the file (the slack bus's angle is its setpoint), and its base voltage base_kv (kV, informative).	Bus(id, kind, vm=1.0, va_deg=0.0, base_kv=0.0)
DcPowerFlowSolution noodl.apps.electrical.power	A solved DC power flow in per unit; tensors may carry leading batch dimensions.	DcPowerFlowSolution(bus_ids, va, gen_buses, pg, branch_rows, pf)
FixedShunt noodl.apps.electrical.power	A fixed admittance from bus to ground, stated as the real power g_mw (MW) it consumes and the reactive power b_mvar (MVAr) it injects at a bus voltage of 1 p.u.	FixedShunt(bus, g_mw, b_mvar)
Generator noodl.apps.electrical.power	A generator on bus: real output p_mw (MW), reactive output q_mvar (MVAr, a starting value), voltage magnitude setpoint vm_set (p.u.) and reactive limits (MVAr).	Generator(bus, p_mw, q_mvar=0.0, vm_set=1.0, in_service=True, q_max_mvar=inf, q_min_mvar=-inf)
Load noodl.apps.electrical.power	A constant-power load on bus, absorbing p_mw (MW) and q_mvar (MVAr).	Load(bus, p_mw, q_mvar)
PowerFlowIndex noodl.apps.electrical.power	How a PowerNetwork maps onto a power-flow model.	PowerFlowIndex(bus_ids, slack_bus, pv_buses, gen_buses, branch_rows, base_mva, fixed_generation, load_buses, shunt_buses)
PowerFlowSolution noodl.apps.electrical.power	A solved power flow in per unit; tensors may carry leading batch dimensions.	PowerFlowSolution(bus_ids, vm, va, gen_buses, pg, qg, branch_rows, sf, st)
PowerNetwork noodl.apps.electrical.power	A power-flow network: buses, branches, generators, loads and fixed shunts in file order, the system base base_mva (MVA), a name and free-form notes (a reader records what it skipped there; they take no part in equality or the hash, so a network is hashable). Construction refuses duplicate bus ids, an unknown bus kind, a nonpositive base and any element on a bus that does not exist.	PowerNetwork(buses, branches, generators, loads=(), shunts=(), base_mva=100.0, name='', notes=<factory>)

Constitutive laws

The relation between the flow through an edge and the potential difference across it.

Name	What it does	How to call it
Capacitance noodl.apps.electrical	A capacitor q = C d(dp)/dt (C in F, initial voltage v0 in V), as companion forms: dc q = 0; initial dp = v0; phasor q = j omega C dp; transient backward Euler q = C (dp - dp_prev) / dt or trapezoidal q + q_prev = 2 C / dt (dp - dp_prev). MSL Basic.Capacitor.	Capacitance(C, *, v0=0.0, kind='capacitor', learnable=False)
ConstantPowerLoad noodl.apps.electrical	A load absorbing the complex power S = P + jQ (W, var; positive = consumption, the power-flow convention), per edge: q = conj(S / dp), on a real layer q = P / dp. scale names a driver whose per-edge values multiply S (a load profile).	ConstantPowerLoad(P, Q=0.0, *, V_nominal=None, linearized=False, direct_current=False, scale=None, kind='load', learnable=False)
DependentSource noodl.apps.electrical	A linear controlled source with edges [control, output] per device: the control port is an open circuit (q1 = 0, voltage control) or a short (dp1 = 0, current control), and the output port imposes dp2 (voltage output) or q2 (current output) as gain times the control voltage dp1 or current q1. Default kinds "vcvs", "vccs", "ccvs", "cccs". MSL Basic.VCV, VCC, CCV, CCC (gain, transconductance in S, transresistance in ohm, current gain).	DependentSource(gain, *, control, output, kind=None, learnable=False)
Impedance noodl.apps.electrical	A series impedance dp = (R + jX) q with the reactance X = omega L - 1/(omega C) (R in ohm, L in H, C in F; C = inf, the default, is no capacitance) at the phasor layer's angular frequency omega. On a real layer (modes dc, initial, transient) it is the resistance dp = R q, and an edge with a reactance (L != 0 or a finite C) is refused; at zero frequency an inductance is a short and a finite capacitance (an open circuit) is refused. R = 0 is a short. Implicit (the flow is an unknown), so a zero resistance needs no special case. MBL AC.OnePhase.Loads.Impedance, DC.Loads.Resistor and the MBL short-circuit loads. learnable applies to R. Linear: valid for any phasor scaling.	Impedance(R, *, L=0.0, C=inf, kind='impedance', learnable=False)
ImpedanceTransformer noodl.apps.electrical	An ideal transformer behind a series primary impedance: dp1 = Z q1 + n dp2, q2 = -n q1 (winding ratio n, primary to secondary voltage; complex primary impedance Z in ohm, per device). Edges [primary node -> reference, secondary node -> reference] per device. Phasor layers only. Linear, so valid for any phasor scaling. MBL AC.OnePhase.Conversion.ACACTransformer (n = VHigh/VLow, Z = \|Zp\| (cos(atan(XoverR)) + j sin(atan(XoverR))), \|Zp\| = VHigh^2 Zperc / VABase).	ImpedanceTransformer(n, impedance, *, kind='impedance_transformer')
Inductance noodl.apps.electrical	An inductor dp = L dq/dt (L in H, initial current i0 in A), as companion forms: dc dp = 0; initial q = i0; phasor dp = j omega L q; transient backward Euler dp = L (q - q_prev) / dt or trapezoidal dp + dp_prev = 2 L / dt (q - q_prev). MSL Basic.Inductor.	Inductance(L, *, i0=0.0, kind='inductor', learnable=False)
JunctionDiode noodl.apps.electrical	A junction diode with a parallel leak: q = Ids (exlin(dp / Vt) - 1) + dp / R, where exlin(x) = exp(x) up to Maxexp and continues linearly above it, exp(Maxexp) (1 + x - Maxexp) (Ids saturation current in A, Vt voltage equivalent of temperature in V, R parallel resistance in ohm). With temperature naming a driver the current follows the junction temperature (below). MSL Semiconductors.Diode. Nonlinear, so not usable in a phasor layer.	JunctionDiode(Ids=1e-06, Vt=0.04, Maxexp=15.0, R=100000000.0, *, temperature=None, N=1.0, TNOM=300.15, XTI=3.0, EG=1.11, kind='diode')
MutualInductance noodl.apps.electrical	Two coupled windings: dp1 = L1 dq1/dt + M dq2/dt, dp2 = M dq1/dt + L2 dq2/dt (L1, L2, M in H; initial currents i0 = (i1, i2) in A, per device or shared). Companion forms as Inductance with the 2x2 inductance matrix. Edges [primary, secondary] per device. MSL Basic.Transformer.	MutualInductance(L1, L2, M, *, i0=(0.0, 0.0), kind='transformer', learnable=False)
PowerConverter noodl.apps.electrical	An AC/DC converter with a constant efficiency, in a phasor layer whose direct-current side is a complex node with zero imaginary part. Edges [ac node -> reference, dc conductor 1 -> dc conductor 2] per device, conductor 2 at the reference potential. Equations, with S_ac = dp_ac conj(q_ac) and P_dc = Re(dp_dc conj(q_dc)) the powers into the two ports: dp_dc = k \|dp_ac\| (with MBL's smoothed modulus reg_root(\|dp_ac\|^2, 1e-5); the imaginary part holds the DC side's at zero) and Re S_ac + P_dc = P_loss, Im S_ac = 0 (unity power factor), with the loss P_loss = (1 - eta) splice(P_dc, Re S_ac, Re q_dc, 0.1): a fraction of the power of whichever side feeds the converter. k (voltage_ratio) is the DC voltage over the AC root-mean-square voltage; eta (efficiency) is between 0 and 1. Valid only with root-mean-square phasors (MBL's, S = V conj(I)): give source amplitudes as RMS values. Phasor layers only. MBL AC.OnePhase.Conversion.ACDCConverter (conversionFactor, eta, ground_DC = true).	PowerConverter(voltage_ratio, efficiency, *, kind='power_converter')
PrescribedCurrent noodl.apps.electrical	An ideal current source: q = offset + amplitude * unit(t) (A) entering pin p whatever the voltage, with the waveform and its phasor as for PrescribedVoltage. MSL Sources.ConstantCurrent, StepCurrent, SineCurrent, PulseCurrent, SignalCurrent. learnable applies to amplitude.	PrescribedCurrent(amplitude, *, waveforms=None, offset=0.0, kind='current_source', learnable=False)
PrescribedVoltage noodl.apps.electrical	An ideal voltage source: dp = offset + amplitude * unit(t) (V), with unit the waveform (Constant by default; one for all edges or one per edge) evaluated at the evaluation time t (s). In phasor mode a Sine(frequency, phase, start_time) source is dp = amplitude * exp(j (phase - omega start_time)) (peak-amplitude, sine-referenced; at the layer's frequency) and a Constant source is dp = amplitude; other waveforms are refused there. MSL Sources.ConstantVoltage, StepVoltage, SineVoltage, PulseVoltage, SignalVoltage. learnable applies to amplitude.	PrescribedVoltage(amplitude, *, waveforms=None, offset=0.0, kind='voltage_source', learnable=False)
Resistance noodl.apps.electrical	A linear resistor: q = dp / R_actual with R_actual = R s (1 + alpha (T - T_ref)) (R in ohm at T_ref in K, alpha in 1/K); T (K) is read per edge from drivers[temperature] when temperature names a driver, else T = T_ref; s is read per edge from drivers[scale] when scale names a driver (a variable resistor whose resistance follows a signal), else s = 1. MSL Basic.Resistor, Basic.VariableResistor (its input R is R s).	Resistance(R, *, alpha=0.0, T_ref=300.15, temperature=None, scale=None, kind='resistor', learnable=False)
SwitchedConductance noodl.apps.electrical	An ideal closing switch: closed q = dp / Ron, open q = Goff dp (Ron in ohm, Goff in S); closed where the control value exceeds 0.5 (or is True). control is a driver key whose last dimension holds one value per switch edge (or one value for all), a single (key, index) pair read by every switch, or a sequence with one entry per edge, each a key (read at index 0) or a (key, index) pair. MSL Ideal.IdealClosingSwitch.	SwitchedConductance(control, *, Ron=1e-05, Goff=1e-05, kind='switch')
TransformerRatio noodl.apps.electrical	An ideal transformer without magnetisation: dp1 = n dp2, q2 = -n q1 (turns ratio n, primary to secondary voltage). Edges [primary p1 -> n1, secondary p2 -> n2] per device. MSL Ideal.IdealTransformer with considerMagnetization = false.	TransformerRatio(n, *, kind='ideal_transformer', learnable=False)
PiBranch noodl.apps.electrical.power	MATPOWER's branch two-port in per unit, [I_f; I_t] = [[Y_ff, Y_ft], [Y_tf, Y_tt]] [V_f; V_t] with Y_s = 1/(r + jx), tau = ratio e^{j shift}, Y_tt = Y_s + jb/2, Y_ff = Y_tt/(tau conj(tau)), Y_ft = -Y_s/conj(tau), Y_tf = -Y_s/tau.	PiBranch(r, x, b, ratio, shift, *, kind='branch', learnable=False)
Shunt noodl.apps.electrical.power	A constant-admittance shunt, i = (g + jb) v (p.u.), per edge bus -> ground: g consumes the real power g \|v\|^2 and a positive b injects the reactive power b \|v\|^2 (a capacitor). MATPOWER's bus Gs, Bs divided by the base power. learnable applies to g and b.	Shunt(g, b, *, kind='shunt', learnable=False)
VoltageControlledGenerator noodl.apps.electrical.power	A generator injecting the real power P (p.u.) at the voltage magnitude V (p.u.), per edge bus -> ground: residual(v, i) = (\|v\| - V) + j (Re(v conj(i)) + P). The edge current i leaves the bus into ground, so the injected complex power is -v conj(i); its real part is P and its reactive part is whatever holds \|v\| = V (a PV bus, without reactive limits). Implicit: the current is an unknown of the layer. Power is v conj(i), so the phasors are root-mean-square. learnable applies to P and V.	VoltageControlledGenerator(P, V, *, kind='generator', learnable=False)

Closures

Functions of the state that compute drivers each step (densities, flows, levels).

Name	What it does	How to call it
HeatedEdge noodl.apps.electrical	A circuit device with a heat port: its edge edge (position in the electrical layer's q), its end nodes p and n (positions in phi), the thermal node heat_node of its heat port (position in the thermal layer's phi), and the per-edge temperature driver temperature_key its law reads, at position slot of that driver.	HeatedEdge(edge, p, n, heat_node, temperature_key, slot)
JouleHeating noodl.apps.electrical	A coupling closure closure(state, drivers) -> driver updates between a circuit layer (electrical) and a thermal layer (thermal) on one network.	JouleHeating(heated, *, electrical='electrical', thermal='thermal', heat_key='thermal.heat', base_temperatures)

Waveforms

Time signals a source follows.

Name	What it does	How to call it
Constant noodl.apps.electrical	A constant: unit value 1 at every time (a DC source: value offset + amplitude).	Constant()
Pulse noodl.apps.electrical	A pulse train: 1 for the first width percent of every period (s) from start_time, else 0; n_periods < 0 repeats for ever, otherwise the pulse train stops after n_periods periods (MSL Blocks.Sources.Pulse).	Pulse(width, period, start_time=0.0, n_periods=-1)
Ramp noodl.apps.electrical	A ramp: 0 before start_time (s), rising linearly to 1 over duration (s), then 1 (MSL Blocks.Sources.Ramp; duration = 0 is a step).	Ramp(duration, start_time=0.0)
Signal noodl.apps.electrical	An external signal: the unit value is read from the driver drivers[key][..., index] at evaluation time (batched like any driver), so a source can follow an external input (MSL SignalVoltage, SignalCurrent). It needs no clock and has no breakpoints.	Signal(key, index=0)
Sine noodl.apps.electrical	A sine wave: 0 before start_time (s), then sin(2 pi frequency (t - start_time) + phase) (frequency in Hz, phase in rad; MSL Blocks.Sources.Sine with continuous = false).	Sine(frequency, phase=0.0, start_time=0.0)
Step noodl.apps.electrical	A step: 0 before start_time (s), 1 from start_time on (MSL Blocks.Sources.Step: if time < startTime then 0 else height).	Step(start_time=0.0)

Files

Readers and writers of other tools' file formats.

Name	What it does	How to call it
read_modelica_circuit noodl.apps.electrical.modelica	Read a noodl-modelica-electrical/1 file into (model, state, drivers, names).	read_modelica_circuit(path, *, substeps=1, omit=())
read_matpower noodl.apps.electrical.power	Read the documented subset of a MATPOWER version 2 case file into a PowerNetwork, in the file's units (MW, MVAr, degrees, p.u. impedances on baseMVA).	read_matpower(path)

Other classes

Supporting types.

Name	What it does	How to call it
CircuitNames noodl.apps.electrical.modelica	What the reader built, by name.	CircuitNames(model, times, grid, restarts, dynamic, phasor, nodes, thermal_nodes, devices, sources, columns)
Column noodl.apps.electrical.modelica	A compared value: part(sum(c * history[key][..., i] for i, c in terms)), with part "real" or "imag" (of a phasor; the real part of a real value is itself).	Column(key, terms, part='real')
ModelicaImportError noodl.apps.electrical.modelica	Raised for a malformed noodl-modelica/1 (building) or noodl-modelica-electrical/1 (circuit) document, or for model content the reader does not support.	ModelicaImportError(...)
MatpowerCaseDigestError noodl.apps.electrical.power	A downloaded or cached MATPOWER case is not the file whose SHA-256 is recorded.	MatpowerCaseDigestError(...)
MatpowerCaseUnavailableError noodl.apps.electrical.power	A MATPOWER case could not be downloaded (no network, or the server refused).	MatpowerCaseUnavailableError(...)

Functions

Calculations and helpers.

Name	What it does	How to call it
ac_sweep noodl.apps.electrical	The sinusoidal steady state of circuit at each of frequencies (Hz), one batched phasor solve: {"frequency": (F,), "electrical.phi": (F, n), "electrical.q": (F, b)}, complex peak-amplitude, sine-referenced phasors (x(t) = \|X\| sin(omega t + arg X)). solve_kwargs, such as method or Newton's atol and rtol, reach the layer solve.	ac_sweep(circuit, frequencies, **solve_kwargs)
device_values noodl.apps.electrical	Per device name, its (voltage, current) (V, A) in state: v = v_p - v_n and the current entering pin p, each of shape (...,) for a one-port device and (..., 2) (port 1, port 2) for a two-port device. A source delivering power has a negative current.	device_values(model, state)
operating_point noodl.apps.electrical	The DC operating point at time t (s): capacitors open, inductors shorted, sources at their value at t (model.steady; solve_kwargs, such as Newton's atol and rtol, reach the layer solve). On a phasor model, the AC steady state.	operating_point(model, drivers, *, t=0.0, **solve_kwargs)
transient noodl.apps.electrical	March the circuit over the time grid times (s), from state at times[0] (usually initial_state), one Model.step per interval.	transient(model, state, drivers, times, *, integration='trapezoidal', **solve_kwargs)
extrapolate noodl.apps.electrical.modelica	Richardson extrapolation of two run histories on the same "time"s, fine with half the step of coarse (twice the substeps), of a method of order order: fine + (fine - coarse)/(2**order - 1) for every entry but "time". For a symmetric second-order method (the building reader's midpoint steps; the circuits' trapezoidal ones, backward Euler after each restart) order=2 removes the leading step-size error. Raises ValueError when the two histories are not on the same times.	extrapolate(coarse, fine, order=2)
simulate_circuit noodl.apps.electrical.modelica	The circuit's history at times (default names.times; each must be a time of names.grid, increasing; a single time may be a scalar): "time" (T,) (the grid times found, a new tensor) and every ".phi" / ".q" state entry the model returns, stacked on dim 0.	simulate_circuit(model, state, drivers, names, *, times=None, **solve_kwargs)
check_power_network noodl.apps.electrical.power	Check that net is a solvable power-flow network and return its PowerFlowIndex.	check_power_network(net, *, dc=False)
dc_power_flow_solution noodl.apps.electrical.power	Bus angles, generation per generator bus and branch flows of a solved DC power flow (model from dc_power_flow).	dc_power_flow_solution(model, state)
matpower_case noodl.apps.electrical.power	The path of MATPOWER 8.1's case name (one of MATPOWER_CASES), downloaded on first use and verified by SHA-256 on every call.	matpower_case(name, *, cache_dir=None)
power_flow_solution noodl.apps.electrical.power	Bus voltages, generation per generator bus and branch end powers of a solved AC power flow (model from build_power_flow).	power_flow_solution(model, state)
solve_power_flow noodl.apps.electrical.power	The solved power flow, AC or DC: model.steady(state, drivers, atol=atol, rtol=rtol, max_iter=max_iter, **solve_kwargs), for a model from build_power_flow or dc_power_flow. For the AC power flow Newton stops when the residual's max-norm (p.u.) is below atol; state is its starting point (the flat start build_power_flow returns, or an earlier solution). The DC power flow is linear: one solve, from the empty state dc_power_flow returns.	solve_power_flow(model, state, drivers, *, atol=1e-11, rtol=0.0, max_iter=30, **solve_kwargs)

Constants and tables

Named values and option tables.

Name	Value
LAYER	'electrical'
BUS_KINDS	3 names: pq, pv, slack
DC_LAYER	'power_dc'
MATPOWER_CASES	table of 5 entries: case9, case14, case30, case118, case9_features
MATPOWER_COMMIT	'1a828c7af590714499284e36ee9c81273388c594'
MATPOWER_RELEASE	'8.1'
POWER_LAYER	'power'